(1) Field of the Invention
This invention relates to fabrication methods used for semiconductor devices, and more specifically a process used to integrate logic and memory devices on a single semiconductor chip.
(2) Description of Prior Art
Advanced semiconductor chips, now being manufactured in industry, are composed of logic or memory devices. Logic devices are used to process information or data, while memory devices are used for data storage. These two types of devices can be found in almost all computers, however they are usually found on specific chips, reserved for either logic or memory applications. In systems in which logic and memory devices are packaged separately, data signals between the two may have to pass through several levels of packaging, which can result in undesirable propagation delays. In addition the manufacturing costs for fabricating wafers producing only logic chips, and wafers with only memory chips, are greater than if both logic and memory applications can be incorporated on the same chip. Therefore for performance and cost reasons the semiconductor industry has been motivated to produce a semiconductor chip with both the desired logic and memory requirements.
The efforts displayed by the semiconductor industry, in attempting to incorporate both logic and memory requirements on a single semiconductor chip have been increasing. Examples of this have been Takemoto, in U.S. Pat. No. 5,066,602, as well as by Vora, in U.S. Pat. No. 5,340,762. These inventions have addressed incorporating bipolar devices and complimentary metal oxide semiconductor, (CMOS), devices, on a single semiconductor chip. However a process for incorporating dynamic random access memory, (DRAM), devices, with logic devices, basically CMOS technology, using a static random access memory, (SRAM), design, has not been evident. This invention will describe a novel fabrication process that allows the memory DRAM devices to be built simultaneously with logic CMOS devices.